1. Field of the Invention
The present invention relates to electronic amplifier circuits. In particular, the present invention relates to an improved input bias current cancellation circuit which cancels out first and second order errors while achieving a wide input voltage range.
2. Description of the Prior Art
Bias current cancellation circuits have been used in the past in amplifier circuits, particularly operational amplifiers. These circuits usually involve monitoring the input current to the differential amplifier NPN transistors, inverting the input current with PNP current mirrors, and injecting the inverted current back into the inputs of the differential amplifier.
The prior art bias current cancellation circuits have, in general, been successful in cancelling first order bias current errors. The biggest contributor to cancellation errors in these circuits is the second order error caused by base current difference in the current mirror PNP transistors. The base current difference is due to the low beta of the PNP transistors.
Another shortcoming of prior art bias current cancellation circuit has been the relatively large amount of head room consumed in order to provide input bias current cancellation. Prior art input bias current cancellation circuits typically limit the input voltage swing to within three to four volts of the power supply rails. Operational amplifiers using input bias current cancellation circuits have typically used .+-.15 volt supply voltages. In order to provide an operational amplifier which operates at much lower supply voltages (such as .+-.5 volts), there is a need for input bias cancellation which does not consume such a large amount of head room while still providing the cancellation.